The present invention relates to an input buffer circuit of a MOS memory circuit, particularly a high speed static RAM, and more particularly to an improvement for reducing the delay of such an input buffer circuit.
FIG. 1 shows a conventional input buffer circuit of a CMOS (complementary metal oxide semiconductor) SRAM (static random access memory) which is directly connectable with a TTL (transistor transistor logic) circuit. As illustrated, the input buffer circuit comprises MOS inverters 31 through 35, comprising P-channel MOS transistors 1, 3, 5, 7, 9 and N-channel MOS transistors 2, 4, 6, 8, 10. In order to permit direct connection with a TTL circuit, the MOS transistors 1 and 2 of the first-stage inverter 31 must have such sizes W that the inverter 31 recognizes "H" when the input at the node Na is 2.2 V or higher and recognizes "L" when the input is 0.8 V or lower, where the power source voltage Vcc is at 5 V.+-.10%. For this reason, the size W of the N-channel side is designed to be larger than in the ordinary CMOS inverters. As a result, the node Nb is more easily pulled low ("L") and is less easily pulled high ("H"). To compensate for this situation, the size W of the N-channel side of the inverter 32 is also set smaller than usual, so that a signal of a normal MOS level is produced at the node Nc.
The inverter 33 is provided merely to invert the signal. The reason for providing this inverter 33 is to enable production of an output signal A and an inverted output signal A, which are supplied as an address signal and an inverted address signal to an address decoder.
The inverters 34 and 35 are the final stages of the input buffer circuit. The nodes Ne and Nf are connected to multiple decoders, so that they are parasitized with very large capacitances including the gate capacitances. The nodes Ne and Nf cannot be inverted quickly even if the sizes W of the transistors 7 through 10 are made relativily large. Moreover, if the sizes W of the transistors 7 through 10 are made large, the nodes Nc and Nd may be parasitized with large capacitances. This is a problem in a large capacity memory.
The conventional input buffer circuit having a construction described above occupies about 25% of the access delay in a high speed SRAM, and forms an obstacle to speed increase.